Clock signals in electronic systems may be used for a variety of purposes such as timing and logical sequencing of integrated circuits. In high speed interconnects used in such electronics system, forwarding a high frequency clock may be a limiting factor of performance. Thus, a lower speed clock may be forwarded on an interconnect followed by recovery of the high frequency clock at a receiving device, using a frequency multiplying device. One traditional technique to perform frequency multiplication is through the use of a phase-locked loop (PLL). However, a PLL may be complex and therefore has cost associated with a relatively large silicon area. Further, PLLs have relatively high jitter (phase noise) which may not be suitable for certain high speed interconnects, particularly those employing forwarded clock architecture.
In another traditional technique for frequency multiplying, the edges of an input clock are cycled multiple times through a multiplexer and using a state machine to control a clock edge before it is compared to a subsequent input edge. However, the multiplexer and/or other circuit elements in this type of cycling frequency multiplier may cause errors in the phases spacing, such that evenly spaced output phases may be difficult or even impossible to obtain. Another traditional technique is to use multipliers after the phase generation. However, this involves use of a separate multiplier for each individual phase which adds complexity and cost.